1. Field of the Invention
The present invention relates to timing circuits, systems, and control methods. In more specific applications, the invention relates to timing adjustment circuits for self-resetting circuits.
2. Description of the Related Art
Microprocessor architectures are continually evolving to improve and extend the capabilities of personal computers. Execution speed, power consumption, and circuit size are aspects of microprocessors and microprocessor performance that are constantly addressed by processor architects and designers in the ongoing quest for an improved product. Execution speed not only depends on the clock rate of a processor, but also upon the speed of interfaces such as cache memories and buses that supply instructions and data for execution by a processor core. The execution speed of microprocessors is heavily analyzed and compared using standard benchmark tests for judging the performance of competing entries into the microprocessor market.
One technique for increasing the operating speed of microprocessors is the usage of fast dynamic logic rather than static logic. However, the usage of dynamic logic involves some risk of incorrect performance due to timing glitches. For example, the detection of one signal of multiple timing signals that may or may not occur, depending on the signals, is a difficult problem. In this example, no signal is inherently generated that indicates that no signals occurred. The function of determining that no signal occurred for a dynamic comparator is a challenge since the signals are dynamic and exist for only a finite pulse width. A first and second signal are compared. If the first signal is reset before the second signal is asserted, no match can possibly be detected.
What is needed is a technique for accurately coordinating timing of self-resetting circuits.